1. Field of the Invention
The present invention relates to a method for fabricating a display device capable of ensuring process stability by removing a metal layer existing in an outermost region of a mother substrate when forming metal patterns.
2. Discussion of the Background
Generally, display devices may be passive or active-matrix devices. A passive-matrix display device does not include thin film transistors (TFTs), while an active-matrix display device does. A passive-matrix display device may be easily fabricated, but it consumes a lot of power, and it is difficult to make it in large sizes. Hence, passive-matrix devices are more useful for small-sized displays. Therefore, active-matrix display devices may be preferred when fabricating large displays.
A conventional active-matrix display device typically includes a plurality of signal lines, such as gate lines for transmitting scan signals and data lines for transmitting data signals.
Further, data pad portions of the data lines may be placed on one side of the mother substrate, and gate pad portions of the gate lines may be placed on an adjacent side. These pad portions may further include electrodes, such as input and output terminals, to apply external power supply and electrical signals.
A pixel region is located at an intersection of the signal lines. The pixel region may comprise one or more TFTs having a semiconductor layer, a gate electrode and source/drain electrodes, a storage portion, which may comprise a lower electrode, an insulating layer, and an upper electrode formed adjacent to a power line and the gate line, and a pixel portion. The pixel portion, which displays an image, may comprise a liquid crystal cell or an organic electroluminescence element.
FIG. 1 is a plan view showing an arrangement of an active-matrix display device. In the display device, a selected region is designated in the form of a reticle on a mother substrate 100, and then each layer is sequentially formed. Some layers, such as an insulating layer, may be formed on the entire surface of the mother substrate 100 without requiring additional patterning. On the other hand, signal lines, such as the data lines, the power line and the gate lines, data pad portions, gate pad portions, the TFT semiconductor layer, the gate electrode, the source/drain electrodes, the upper and lower electrodes of the storage portion, and a plurality of other metal wirings may require several patterning processes using masks.
A conventional patterning process uses a photolithography process, in which a metal layer to be patterned is formed on the entire surface of the mother substrate, and photoresist PR, which is a photosensitive or etching material, may be deposited on the metal layer. After exposure and development steps, wet or dry etching may be performed using the photoresist as a mask.
FIG. 2A, which is an enlarged plan view of the region A of FIG. 1, shows an exemplary mask design after depositing photoresist PR on a metal layer 120 in a sub-display device 110. First, a positive photoresist may be deposited on the entire surface of the mother substrate 100, and a photoresist PR pattern may be obtained by illuminating an exposure shot into a selected region a of the sub-display device 110 using a mask. An etching process may then be performed to obtain a metal pattern. When etching with the positive photoresist, the metal layer is not removed in a region where the photoresist pattern is formed, but it is removed in a region where the photoresist pattern is not formed. In the above patterning process, the exposure and patterning processes are not performed in an outermost region b of the mother substrate 100, so that the metal layer on the mother substrate 100 at the outermost region b remains even after forming the metal pattern.
FIG. 2B, which is a cross-sectional view taken along the line I-I′ of FIG. 2A, shows the metal pattern obtained by exposure and etching processes. Referring to FIG. 2B, when forming a desired metal pattern in the selected region a, the metal pattern also remains in the outermost region b of the mother substrate 100. The metal pattern in the outermost region b may eventually be cut or removed after final processing.
However, the metal pattern remaining in the outermost region b may not adhere to the mother substrate 100 as strongly as the metal pattern formed in the selected region a. Since distortion of the mother substrate 100 determines stress applied to the metal layer 120, stress applied per unit area may increase towards the substrate's outer region b, which may cause the relatively weaker adhesion of the deposited metal layer 120 in the outermost region b.
FIG. 3 is a cross-sectional view showing how the metal layer 120 might be lifted off of the mother substrate 100. As FIG. 3 shows, high stress may strip part of the metal layer 120 in the outermost region b from the mother substrate 100. Consequently, the metal layer 120 may attach to a surface of a sub-display device 110 in the mother substrate 100, thereby causing a defect such as a short circuit. Further, the deposited metal layer 120 may be single or multi-layered, comprising different types of metal depending on a resistance value, work function and correlation with the electrode of the wiring. Considering the adhesion between different types of metal, the lift off of the metal layer 120 may become more serious. Consequently, the TFT fabrication process may become more unstable, thereby increasing a failure rate of when fabricating display devices.
This problem may worsen when performing multiple patterning processes to form a plurality of signal lines, a pad portion, a gate electrode, source/drain electrodes and a plurality of metal wirings.
Moreover, the photoresist may also increase the stress of the metal layer in the outermost region b. Generally, the photoresist may be deposited by spin coating, and the photoresist in the outer portion b may be deposited about 150 to 200% thicker than desired. This increased thickness may cause undesired photoresist to remain in the outermost region b, even after subsequent exposure and etching processes. Hence, photoresist residue may attach to the surface of the TFT in a subsequent process and may increase the stress applied to the metal layer formed in the outermost region b. Therefore, the metal layer 120 in the outermost region b may be stripped off during a semiconductor fabrication process, which may cause product failure.
For the reasons noted above, it is desirable to reduce defects, occurring during device fabrication, involving a metal layer in the outermost region of the mother substrate.